This invention relates to improvements in micro-BGA chip scale packaging.
Chip scale packaging (CSP) of integrated circuits is a widely accepted electronic systems packaging technology. Ball grid array (BGA) packaging, such as the xcexcBGA(copyright) package developed by Tessera Technologies of San Jose, Calif., is often looked to as the chip scale packaging (CSP) method of choice, it being valued for accommodating the mismatch in coefficients of thermal expansion (CTE) between silicon and commonly used substrates, such as FR-4 epoxy circuit boards.
The fundamentals of micro-BGA technology are generally summarized in the six patents set forth below, the disclosures of which are incorporated by reference herein in their entirety Khandros et al., U.S. Pat. No. 5,148,265, for SEMICONDUCTOR CHIP ASSEMBLIES WITH FAN-IN LEADS, discloses a semiconductor chip having contacts on the periphery of its top surface is provided with an interposer overlying the central portion of the top surface. Peripheral contact leads extend inwardly from the peripheral contacts to central terminals on the interposer. The terminals on the interposer may be connected to a substrate using techniques commonly employed in surface mounting of electrical devices, such as solder bonding. The leads, and preferably the interposer, are flexible so that the terminals are movable with respect to the contacts on the chip, to compensate for differential thermal expansion of the chip and substrate. The terminals on the interposer may be disposed in an area array having terminals disposed at substantially equal spacings throughout the area of the interposer, thus providing substantial distances between the terminals while accommodating all of the terminals in an area approximately the same size as the area of the chip itself. The interposer may be provided with a compliant layer disposed between the terminals and the chip to permit slight vertical movement of the terminals towards the chip during testing operations. The chip and interposer assembly may be electrically tested prior to assembly to the substrate. A compliant layer disposed between the terminals and the chip permits slight vertical movement of the terminals towards the chip during testing operations, in which the terminals on the interposer are engaged with an assembly of test probes. The entire assembly is compact.
Khandros et al., U.S. Pat. No. 5,148,266, for SEMICONDUCTOR CHIP ASSEMBLIES HAVING INTERPOSER AND FLEXIBLE LEAD, discloses a semiconductor chip assembly is mounted to contact pads in a compact area array. An interposer is disposed between the chip and the substrate. The contacts on the chip are connected to terminals on the interposer by flexible leads extending through apertures in the interposer. The terminals on the interposer in turn are bonded to the contact pads on the substrate. Flexibility of the leads permits relative movement of the contacts on the chip relative to the terminals and the contact pads of the substrate and hence relieves the stresses caused by differential thermal expansion. The arrangement provides a compact structure similar to that achieved through flip-chip bonding, but with markedly increased resistance to thermal cycling damage.
DiStefano et al., U.S. Pat. No. 5,455,390, for a MICROELECTRONICS UNIT MOUNTING WITH MULTIPLE LEAD BONDING, discloses a component for mounting semiconductor chips or other microelectronic units includes a flexible top sheet with an array of terminals on it, and with flexible leads extending downwardly from the terminals. A compliant dielectric support layer surrounds the leads, holding the lead tips in precise locations. The leads are desirably formed from wire such as gold wire, and have eutectic bonding alloy on their tips. The component can be laminated to a chip or other unit under heat and pressure to form a complete subassembly with no need for individual bonding to the contacts of the chip. The subassembly can be tested readily and provides compensation for thermal expansion.
Distefano et al., U.S. Pat. No. 5,518,964, for a MICROELECTRONIC MOUNTING WITH MULTIPLE LEAD DEFORMATION AND BONDING, discloses a microelectronic connection component includes a dielectric sheet having an area array of elongated, strip-like leads. Each lead has a terminal end fastened to the sheet and a tip end detachable from the sheet. Each lead extends horizontally parallel to the sheet, from its terminal end to its tip end. The tip ends are attached to a second element, such as another dielectric sheet or a semiconductor wafer. The first and second elements are then moved relative to one another to advance the tip end of each lead vertically away from the dielectric sheet and deform the leads into a bent, vertically extensive configuration. The preferred structures provide semiconductor chip assemblies with a planar area array of contacts on the chip, an array of terminals on the sheet positioned so that each terminal is substantially over the corresponding contact, and an array of metal S-shaped ribbons connected between the terminals and contacts. A compliant dielectric material may be provided between the sheet and chip, substantially surrounding the S-shaped ribbons.
Khandros et al., U.S. Pat. No. 5,679,997, for a SEMICONDUCTOR CHIP ASSEMBLIES, METHODS OF MAKING SAME AND COMPONENTS FOR SAME, discloses semiconductor chip assemblies incorporating flexible, sheet-like elements having terminals thereon overlying the front or rear face of the chip to provide a compact unit. The terminals on the sheet-like element are movable with respect to the chip, so as to compensate for thermal expansion. A resilient element such as a compliant layer interposed between the chip and terminals permits independent movement of the individual terminals toward the chip driving engagement with a test probe assembly so as to permit reliable engagement despite tolerances.
Khandros et al., U.S. Pat. No. 5,685,855, for a WAFER-SCALE TECHNIQUES FOR FABRICATION OF SEMICONDUCTOR CHIP ASSEMBLIES, discloses a method wherein semiconductor chip assemblies are fabricated by assembling flexible, sheetlike elements bearing terminals to a wafer, connecting the terminals of each sheetlike element to contacts on the chip, and subsequently severing the chips from the wafer to provide individual assemblies. Each assembly includes a sheetlike element and a chip, arranged so that the terminals on the flexible element are movable with respect to the chip.
Disclosed is a method of ball grid array packaging, comprising the steps of providing a semiconductor die having a metal conductors thereon, covering said metal conductors with an insulative layer, etching through said insulative layer so as to provide one or more openings to said metal conductors, depositing a compliant material layer, etching through said compliant material layer so as to provide one or more openings to said metal conductors, depositing a substantially homogenous conductive layer, patterning said conductive layer so as to bring at least one of said metal conductors in electrical contact with one or more pads, each said pad comprising a portion of said conductive layer disposed upon said compliant material, and providing solder balls disposed upon said pads.
Another aspect of the method further comprises the step of depositing a passivation layer prior to said deposition of said compliant material layer.
In another aspect of the method said passivation layer comprises a silicon nitride layer atop a silicon oxide layer.
In another aspect of the method said passiviation layer comprises borosilicate glass.
In another aspect of the method said metal conductors are a metallic damascene layer.
In another aspect of the method said metal conductors comprise copper.
In another aspect of the method said insulative layer comprises a silicon oxide layer atop a silicon nitride layer.
In another aspect of the method said step of etching through said compliant material is executed in a manner effective in not etching said insulative layer and in forming vias of greater width than said openings through said insulative layer.
In another aspect of the method said conductive layer comprises aluminum and copper.
Another aspect of the method further comprising the step of depositing a barrier layer prior to said deposition of said conductive layer.
In another aspect of the method said barrier layer comprises at least one of tantalum nitride, titanium nitride, or tungsten nitride.
In another aspect of the method said compliant material comprises a poly-imide.
Disclosed is a ball grid array package, comprising a semiconductor die having a compliant layer thereon and metallic circuitry therein, a substantially homogenous conductive layer deposited upon said compliant material and patterned so as to bring at least one point of said metallic circuitry into electrical contact with one or more pads, each said pad comprising a portion of said conductive layer disposed upon said compliant material, and one or more solder balls disposed upon said pads.
In another aspect of the invention said metal circuitry is a metallic damascene layer.
In another aspect of the invention said metal circuitry comprises copper.
In another aspect of the invention said conductive layer is deposited in-vias, said vias insulated from said metal circuitry by an insulative layer, said insulative layer having an openings therethrough to permit electrical contact between said metal circuitry and said conductive layer.
In another aspect of the invention said conductive layer comprises aluminum and copper.
Another aspect of the invention further comprises a barrier layer interposed between said conductive layer and said semiconductor die.
In another aspect of the invention said barrier layer comprises at least one of tantalum nitride, titanium nitride, or tungsten nitride.
In another aspect of the invention said compliant material comprises a poly-imide.